
module inst_fetch(
	input wire clk_i,
        input wire rst_i,
	output wire[31:0] inst_o
);

wire[5:0] pc;
wire rom_ce;


pc_reg pc_reg0(.clk_i(clk_i), .rst_i(rst_i), .pc_o(pc), .ce_o(rom_ce));

inst_rom rom0(.ce(rom_ce), .addr(pc), .inst(inst_o));
endmodule
